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6–2
Chapter 6: Performing SignalTap II Logic Analysis
4. Choose one of the JTAG cable ports in the Signal Compiler dialog box or the
SignalTap II Logic Analyzer dialog box.
5. Using Signal Compiler , synthesize your model, perform compilation in the
Quartus II software, and download your design into the DSP development board
(starter or professional).
6. Specify the required trigger conditions in the SignalTap II Logic Analyzer
block.
f For details of the SignalTap II Logic Analyzer and SignalTap II Node blocks, refer
to the descriptions of these blocks in the AltLab Library chapter in the DSP Builder
Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook .
SignalTap II Nodes
A node represents a wire carrying a signal that travels between different logical
components of a design file. The SignalTap II logic analyzer can capture signals from
any internal device node in a design file, including I/O pins.
The SignalTap II logic analyzer can analyze up to 128 internal nodes or I/O elements.
As more it capture more signals, it uses more logic elements (LEs) or embedded
system blocks (ESBs).
Before capturing signals, assign each node to analyze to a SignalTap II logic analyzer
input channel. To assign a node to an input channel, you must connect it to a
SignalTap II Node block.
SignalTap II Trigger Conditions
The trigger pattern describes a logic event in terms of logic levels or edges. The
SignalTap II logic analyzer uses a comparison register to recognize the moment when
the input signals match the data specified in the trigger pattern.
The trigger pattern comprises a logic condition for each input signal. By default, all
signal conditions for the trigger pattern are set to Don’t Care , masking them from
trigger recognition. You can select one of the following logic conditions for each input
signal in the trigger pattern:
■
■
■
■
■
■
Don’t care
Low
High
Rising edge
Falling edge
Either edge
The SignalTap II logic analyzer triggers when it detects the trigger pattern on the
input signals.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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